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Low Power CMOS SRAM 32K X8 Bits
Features:
* Vcc operation voltage : 2.0V ~ 3.6V * Low power consumption : 10mA (Max.) operating current 0.1uA (Typ.) CMOS standby current * High Speed Access time : 35ns (Max.) at Vcc = 2.7V 55ns (Max.) at Vcc = 2.7V 70ns (Max.) at Vcc = 2.0V * Automatic power down when chip is deselected * Three state outputs and TTL compatible * Data retention supply voltage as low as 1.2V * Easy expansion with CE\ and OE\ options
UC62LV0256 -35/-55/-70
Description
The UC62LV0256 is a high performance, very low power CMOS Static Random Access Memory organized as 32,768 words by 8 bits and operates from a wide range of 2.0V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1uA and maximum access time of 70ns in 2.0V operation. Easy memory expansion is provided enable (CE), and active LOW output enable (OE) and three-state output drivers. The UC62LV0256 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The UC62LV0256 is available in the JEDEC standard 28 pin 330mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP and 8mmx13.4mm TSOP (normal type).
PRODUCT FAMILY
Product Family
UC62LV0256BC UC62LV0256CC UC62LV0256DC UC62LV0256EC UC62LV0256AC UC62LV0256BI UC62LV0256CI UC62LV0256DI UC62LV0256EI UC62LV0256AI
Operating Temperature
Vcc Range
Speed (ns) Vcc=2.7V
STANDBY Vcc=3.0V
Power Consumption VCC=3.6V Operating (Max) 35ns 55ns 70ns
Package Type
SOP-28 TSOP-28 PDIP-28 SOJ-28 DICE SOP-28 TSOP-28 PDIP-28 SOJ-28 DICE
0J ~ 70J
2.0V ~ 3.6V
-35/ -55/ -70
0.1uA
17mA
13mA
10mA
-25J ~ 85
2.0V ~ 3.6V
-35/ -55/ -70
0.1uA
17mA
13mA
10mA
PIN CONFIGURATIONS
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14
BLOCK DIAGRAM
VCC WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2
ROW DECODER
1 2 3 4 5 6 7 8 9 10 11 12 13 14
UC62LV0256BI UC62LV0256DI UC62LV0256EI UC62LV0256BC UC62LV0256DC UC62LV0256EC
28 27 26 25 24 23 22 21 20 19 18 17 16 15
ROW Address
ADDRESS INPUT BUFFER
CE WE OE
A0 - A14
MEMORY ARRAY 32K X 8 Bits
COL Address
COLUMN DECODER
CE WE OE
SENSE AMPLIFIER & WRITE DRIVER
CONTROL INPUT BUFFER
CONTROL BLOCK
X8
I/O BUFFER
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
UC62LV0256CC UC62LV0256CI
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Revision 2.0 PAGE 1
Low Power CMOS SRAM 32K X8 Bits
PIN DESCRIPTION
Name A0 - A14 CE\ Type Input Input Function
Address inputs for selecting one of the 32768 x 8 bit words in the RAM
UC62LV0256 -35/-55/-70
CE\ is active LOW. Chip enable must be active when data read from or write to the device. If chip enable is not active, the device is deselected and not in a standby power down mode. The DQ pins will be in high impedance state when the device is deselected.
WE\
Input
The Write enable input is active LOW and controls read and write operations. With the chip selected, when WE\ is HIGH and OE\ is LOW, output data will be present on the DQ pins, when WE\ is LOW, the data present on the DQ pins will be written into the selected memory location.
OE\
Input
The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE\ is inactive.
DQ0 - DQ7 Vcc Gnd
I/O Power Power
These 8 bi0directional ports are used to read data from or write data into the RAM. Power Supply Ground
TRUTH TABLE
Mode
Not Selected Output Disabled Read Write
WE\
X H H L
CE\
H L L L
OE\
X H L X
I/O state
High Z High Z DOUT DIN
Vcc Current
ISB,ISB1 ICC ICC ICC
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL VTERM TBIAS TSTG PT IOUT PARAMETER Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current RATING -0.5 to VCC+0.5 -40 to 125 -50 to 150 50mW 10 UNIT V J J W mA
OPERATING RANGE
RANGE
Commercial Industrial
AMBIENT TEMPERATURE
0J to 70J -25J to 85J
VCC
2.0V~ 3.6V 2.0V ~ 3.6V
CAPACITANCE(1)(TA=25J ,f=1.0MHz)
SYMBOL PARAMETER CONDITIONS MAX. UNIT Input VIN=0V 6 pF CIN Capacitance Input/Output VDQ 8 pF CDQ Capacitance 1. This parameter is guaranteed and not 100% tested.
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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Revision 2.0 PAGE 2
Low Power CMOS SRAM 32K X8 Bits
UC62LV0256 -35/-55/-70
DC ELECTRICAL CHARACTERISTICS (TA=-25J to 85J , VCC=2.0V to 3.6V)
Symbol
VIL VIH IL IOL VOL VOH ICC ISB1 ISB2
Comment
Guaranteed Input Low (2) Voltage Guaranteed Input High (2) Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current TTL Standby Current CMOS Standby Current
Test Condition
VCC=2.7V VCC=3.6V VCC=3.6V VIN=0V to VCC VCC=3.6V CE\=VIH or OE\=VIH VIO=0V t VCC VCC=3.6V, IOL=2 mA VCC=3.0V, IOH=-1 mA CE\=VIL,IDQ=0mA, F=Fmax CE\=VIH, VIN=VIH to VIL CE\U VCC-0.2V, VIN=VCC-0.2V to 0.2V
(3)
MIN.
-0.5 2.0 2.4 -
TYP.(1)
0.1uA
MAX.
0.8 Vcc-0.2 1 1 0.4 10 1 1
UNITS
V V uA uA V V mA mA uA
1. Typical characteristics are at TA = 25J. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC, tRC=70ns .
DATA RETENTION CHARACTERISTICS ( TA=0J to 70J )
Symbol VDR ICCDR tDR tR 1. 2. Comment VCC to Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Test Condition CE\U VCC - 0.2V VINU VCC-0.2V or VINO 0.2V CE\U VCC - 0.2V VINU VCC-0.2V or VINO 0.2V See Retention Waveform TRC
(2)
MIN. 1.2 0
TYP. -
(1)
MAX. 0.5 -
UNITS V uA ns ns
0.05 -
VCC = 1.5V, TA = 25J . tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM(1) (CE\ Controlled)
Vcc CE
tCDR VIH
Data Retention Mode VDR >= 1. 2V CE >= VCC - 0. 2V
tR VIH
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Revision 2.0 PAGE 3
Low Power CMOS SRAM 32K X8 Bits
UC62LV0256 -35/-55/-70
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level VCC/0V 1V/ns 0.5VCC
KEY TO SWITCHING WAVEFORMS
WAVEFORMS INPUTS
MUST BE STEADY
MAY CHANGE FROM H TO L
1269
OUTPUTS
MUST BE STEADY
WILL BE CHANGE FROM H TO L
WILL BE CHANGE FROM L TO H
CHANGE STATE UNKNOWN
AC TEST LOADS AND WAVEFORMS
3.3V
INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE
3.3V
1269
OUTPUT
OUTPUT
MAY CHANGE FROM L TO H
DON'T CARE ANY CHANGE PERMITTED
1404
FIGURE 1A
FIGURE 1B
DOES NOT APPLY
1404
100pF
5pF
TERMINAL EQUIVALENT 667 OUTPUT 1.73V
CENTER LINE IS HIGH IMPEDANCE OFF STATE
ALL INPUT PULSES
VCC
GND
10% 90% 90% 10%
FIGURE 2
5ns
5ns
AC ELECTRICAL CHARACTERISTICS (TA=0J to 70J , VCC=3.0V)
READ CYCLE
JEDEC PARAMETER NAME
tAVAX tAVQV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tAXOX
PARAMETER NAME
tRC tAA tCE tOE tCLZ tOLZ tCHZ tOHZ tOH
DESCRIPTION
Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Output Enable to Output Low Z Chip Deselect to Output in High Z Output Disable to Output in High Z Address Chang to Output Change
UC62LV0256-35
Min 35 5 5 0 0 10 Typ Max 35 35 15 35 20 -
UC62LV0256-70
Min 70 10 10 0 0 10 Typ Max 70 70 50 35 30 -
UNIT
ns ns ns ns ns ns ns ns ns
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Revision 2.0 PAGE 4
Low Power CMOS SRAM 32K X8 Bits
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
tRC ADDRESS tOH DOUT tAA
UC62LV0256 -35/-55/-70
tOH
READ CYCLE2 (1,3,4)
CE tCLZ (5) DOUT tCE tCHZ (5)
READ CYCLE3 (1,4)
tRC ADDRESS tAA OE tOE CE tOLZ tCLZ (5) DOUT
NOTES: 1. WE\ is high in read cycle. 2. Device is continuously selected when CE\ = VIL 3. Address valid prior to or coincident with CE\ transition low. 4. OE\ = VIL. 5. Transition is measured 500mV from steady state with CL=5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested.
tOH
tOHZ (1,5)
tCE
tCHZ (5)
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Revision 2.0 PAGE 5
Low Power CMOS SRAM 32K X8 Bits
UC62LV0256 -35/-55/-70
AC ELECTRICAL CHARACTERISTICS (TA=0J to 70J , VCC=3.0V)
WRITE CYCLE
JEDEC PARAMETER NAME
tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tWLOZ tDVWH tWHDX tGHOZ tWHQX
PARAMETER NAME
tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOHZ tOW
DESCRIPTION
Write Cycle Time Chip Select to END of Write Address Setup Time Address valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold Time for Write End Output Disable to Output In High Z End of Write to Output Active
UC62LV0256-35
Min 35 35 0 35 20 0 15 0 0 5 Typ 15 Max 15
UC62LV0256-70
Min 70 70 0 70 50 0 40 0 0 5 Typ 30 Max 30
UNIT
ns ns ns ns ns ns ns ns ns ns ns
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITECYCLE1(1)
tWC ADDRESS tAW OE tCW(11) CE tAS
(4,10)
tWP(2) tOHZ
WE
DOUT tDW DIN tDH
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Revision 2.0 PAGE 6
Low Power CMOS SRAM 32K X8 Bits
WRITE CYCLE2(1,6)
tWC ADDRESS tAW CE tAS tWP(2) WE tWHZ DOUT tDW DIN tCW(11)
UC62LV0256 -35/-55/-70
tOH (7) tDH (8)
NOTES: 1. WE\ must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals must be active to initiate a write and any one can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE\ or WE\ going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\ transition, output remain in a high impedance state. 6. OE\ is continuously low (OE\ = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write.
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Revision 2.0 PAGE 7
Low Power CMOS SRAM 32K X8 Bits
UC62LV0256 -35/-55/-70
ORDERING INFORMATION
UC62LV0256AB -- YY
A => PACKAGE A : DICE B : 28 SOP - 330mil C : 28 TSOP - 8X13.4mm D : 28 PDIP - 600mil E : 28 SOJ - 300mil B => GRADE C :COMMERCIAL; 0 ~ 70J I : INDUSTRIAL; -25 ~ 85J YY => SPEED 70 : 70ns 55 : 55ns 35 : 35ns PACKAGE DIMENSIONS
28 15 0.020O 0.005X45" "A" UNIT SYMBOL A A1 A2 b b1 c A c1 D E c 7X(4X) L1 DETAIL "A" (2:1) A L E1 e L L1 y c
INCH
0.106O 0.006 0.009O 0.005 0.098O 0.005 0.014 ~ 0.020 0.014 ~ 0.020 0.008 ~ 0.012 0.008 ~ 0.011 0.713O 0.005 0.331O 0.005 0.465O 0.012 0.050O 0.006 0.0380O 0.0104 0.0677O 0.0079 0.004 Max. 0X ~ 10X
MM
2.692O 0.152 0.226O 0.124 2.489O 0.127 0.35 ~ 0.50 0.35 ~ 0.45 0.20 ~ 0.32 0.20 ~ 0.28 18.110O 0.127 8.407O 0.127 11.811O 0.305 1.270O 0.152 0.964O 0.264 1.72O 0.2 0.1 Max. 0X ~ 10X
1 e D b
14
A2
E E1
A
b WITH PLATING
Seating Plane "y"
A1
c c1 BASE METAL b1 SECTION A-A
SOP - 28
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Revision 2.0 PAGE 8
Low Power CMOS SRAM 32K X8 Bits
PACKAGE DIMENSIONS (continued)
12X(2X) 12X(2X) e HD
E
UC62LV0256 -35/-55/-70
b
1
28
UNIT SYMBOL A A1 SEATING PLANE A2 b b1 c GAUGE PLANE c1 D E e HD L L1 y c
INCH
0.0433O 0.004 0.0045O 0.0026 0.039O 0.002 0.009O 0.020 0.008O 0.001 0.004 ~ 0.008 0.004 ~ 0.006 0.465O 0.004 0.315O 0.004 0.22O 0.004 0.528O 0.008 0.0197O 0.008 0.0315O 0.004 0.004 Max. 0X ~ 8X
MM
1.10O 0.10 0.226O 0.124 1.00O 0.05 0.22O 0.05 0.20O 0.03 0.10 ~ 0.21 0.10 ~ 0.16 11.80O 0.10 8.00O 0.10 0.55O 0.10 13.40O 0.20 0.50O 0.20 0.80O 0.10 0.1 Max. 0X ~ 8X
14
15
12X(2X)
A A2
D
"A" A c
A1
0.254
A 12X(2X) L L1 "A" DETAIL VIEW b
14
15
SEATING PLANE
WITH PLATING c c1 1 28 BASE METAL b1 SECTION A-A
TSOP - 28
UNIT SYMBOL A1 A2 D B B1 c D E E1 e eB S B B1 e L S Q1 c E 5X ~ 7X
Q1 A2
INCH(BASE)
0.010(MIN) 0.150O 0.005 0.018O 0.005 0.060O 0.010 0.010O 0.004 0.146O 0.005 0.600O 0.010 0.544O 0.004 0.100(TYP) 0.640O 0.020 0.130O 0.010 0.080O 0.010 0.070O 0.005 6 X O 3X
MM
0.254(MIN) 3.810O 0.127 0.457O 0.127 1.524O 0.254 0.254O 0.102 37.084O 0.127 15.240O 0.254 13.818O 0.102 2.540(TYP) 16.256O 0.508 3.302O 0.254 2.032O 0.254 1.778O 0.127 6 X O 3X
5X ~ 7X
c
A1
L
E1 eB c
PDIP - 28
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Revision 2.0 PAGE 9
Low Power CMOS SRAM 32K X8 Bits
PACKAGE DIMENSIONS (continued)
UNIT SYMBOL A A1 28 15 A2 b1 b c D E e e1 HE L S y c
UC62LV0256 -35/-55/-70
INCH
Min -0.027 0.095 0.026 0.016 0.008 -0.295 0.044 0.245 0.327 0.077 --0X Nom --0.1 0.028 0.018 0.010 0.710 0.300 0.050 0.265 0.337 0.087 ---Max 0.140 -0.105 0.032 0.022 0.014 0.730 0.305 0.056 0.285 0.347 0.097 0.045 0.004 10X Min -0.69 2.41 0.66 0.41 0.20 -7.49 1.12 6.22 8.31 1.96 --0X
MM
Nom --2.54 0.71 0.46 0.25 18.03 7.62 1.27 6.73 8.56 2.21 ---Max 0.140 -2.67 0.81 0.56 0.36 18.54 7.75 1.42 7.24 8.81 2.46 1.14 0.10 10X
1
14
D
E1
E
S Seating Plane
b b1
A1
e
e1
SOJ - 28
Note: 1. Dimension D Max & s include mold flash or tie bar burns. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimension D & E include mold mismatch and are determined at the mold parting line. 4. Controlling dimension: Inch 5. General appearance spec. should be based on final visual inspection spec.
A2
A
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L
c
Revision 2.0 PAGE 10

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